Dynamic Binary Translation and Optimization

We describe a VLIW architecture designed speci cally as a target for dynamic compilation of an existing instruction set architecture. This design approach o ers the simplicity and high performance of statically scheduled architectures, achieves compatibility with an established architecture, and makes use of dynamic adaptation. Thus, the original architecture is implemented using dynamic compilation, a process we refer to as DAISY (Dynamically Architected Instruction Set from Yorktown). The dynamic compiler exploits runtime pro le information to optimize translations so as to extract instruction level parallelism. This work reports di erent design trade-o s in the DAISY system, and their impact on nal system performance. The results show high degrees of instruction parallelism with reasonable translation overhead and memory usage.